ISMVL-2003 Program

May 17, Morning: 9:10~10:30 & 10:40~12:20
Opening address
1. Invited Talk. Chair M. Mukaidono
Lotfi A. Zadeh
Fuzzy Logic as a Basis for a Theory of Hierarchical Definability
2a: Logic Design I. Chair M. Perkowski
Dubrova, E.
Implementation of Multiple-Valued Functions Using Literal Splitting Technique
Takagi, N., Nakashima, K.
Hyperoperations on {0,1,2} Based on Min, Max, and Universal Literal Operations
Yoshinori Yamamoto
An extension of ternary majority function and its application to evolvable hardware
Jong-Hak Hwang, Kyung-Jae Moon, Seung-Yong Park, Heung Soo Kim
A New Construction of the Irreducible Polynomial for Parallel Multiplier over GF(2m)

2b: Functional Expressions. Chair G. Pogosyan
Adams, K.J., McGregor, J.
New Information on the Effectiveness of Different Reed-Muller Algebras on the Representation of Quaternary Functions
Falkowski, B.J., Fu, Cheng
Polynomial Expansions over GF(3) based on Fastest Transformation
Chul-U Lee, Gee-Young Byun, Boo-Sik Shin, Jae-Hwan Sim, Heung Soo Kim
The Generation Circulation Method to Generalized Reed-Muller Coefficients over GF(3)
Dragan Jankovic, Radomir S. Stankovic, Claudio Moraga
Optimization of GF(4) expressions using the extended dual polarity property

May 17, Afternoon: 13:30~15:35 & 15:55~18:00
3a: Fuzzy Logic. Chair D. Simovici
I. Perfilieva
Normal Forms for Fuzzy Logic Functions
Vilém Novak
On Fuzzy (Lukasiewicz) Type Theory
Gottwald, S.
Universes of Fuzzy Sets – A Short Survey
Khosro Soleimani, M. Mashinchi, H.R. Malski
Fixed Points for Fuzzy Rule Bases and Fuzzy Chaining Syllogism
Soyji Kobashi, Katsuya Kondo, Yutaka Hata
Automated Finding of the Willis Ring in MR Angiography Images Using Fuzzy Knowledge Base

3b: LSI Design. Chair O. Ishizuka
J. Sakiyama, T. Aoki, T. Higuchi
Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms
Takahiro Hanyu, Tomohiro Takahashiz, Michitaka Kameyama
Bidirectional Data Transfer Based Asynchronous VLSI System Using Multiple-Valued Current Mode Logic
E. Kinvi-Boh, Michel Aline, Olivier Sentieys
MVL Circuit Design and Characterization in SUS-LOC Technology
H. H. Babu, R. Islam, A. A. Ali, M. S. Akon, A. Rahaman, F. Islam
A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits
Gi Soo Na, Sang Wan Kim, Jae-Sock Choi, Heung Soo Kim
Generation method of the Generalized Reed-Muller Coefficient Using the Triangle Cell

4a: Logic Design II. Chair C. Moraga
Sasao, T.
A Cascade Realization of Two-Valued Input Multiple-Valued Output Functions Using Decomposition of Group Functions
Seok-Bum Ko, Jien-Chung Lo
A novel technology mapping for AND/XOR expression
Al-Rabadi, A.
Iterative Symmetry Indices Decomposition for Logic Synthesis in Three-Dimensional Space
Khan, M.H.A., Perkowski, M., Kertnopf, P.
Multi-Output Galois Field Sum of Product (GFSOP) Synthesis with New Quantum Cascades
Xie, S., Rahardja, S., Gu, Z.
Relationship between UCHT and FFT

4b: Logics and Algebras. Chair V. Novak
Simovici, D.
Several Remarks on Non-Boolean Functions over Boolean Algebras
Ninomiya, T., Mukaidono, M.
Complete and Independent Sets of Axioms of Boolean Algebra
Baaz, M. Preining, N., Zach, R.
Characterization of the Axiomatizable Prenex Fragments of First-Order Godel Logics
Ansotegui, C., Manya, F.
New Logical and Complexity Results for Signed-SAT
Fermueller, Ch., Ciabattoni, A.
From Intuitionistic Logic to Godel-Dummett Logic via Parallel Dialogue Games

May 18, Morning: 9:10~10:10 & 10:30~12:10
5: Invited Talk. Chair T. Waho
Tetsuya Asai and Yoshihito Amemiya
Biomorphic Analog Devices based on Reaction-Diffusion Systems

6a: LSI Circuits. Chair S. Ali
Takahiro Hanyu, Akira Mochizuki and Michitaka Kameyama
Multiple-Valued Dynamic Source-Coupled Logic
K. Degawa, T. Aoki, and T. Higuchi
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic
Sung Il Han, Young Hee Choi, Hyeon-Kyeong Seong and Heung Soo Kim
A Study on the Design of Flash Analog to Quaternary Converter Using DLC Comparator
Omid Mirmotahari and Yngvar Berg
A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate Latch

6b: Decision Diagrams I. Chair J. T. Butler
Miller, D.M., Dueck, G.
On the Size of Multiple-Valued Decision Diagrams
Popel, D.V., Drechsler, R.
Efficient Minimization of Multiple-valued Decision Diagrams for Incompletely Specified Functions
Nagayama, S., Sasao, T.
Compact Representations of Logic Functions using Heterogeneous MDDs
Freivalds, R., Miyakawa, M., Rosenberg, I.G.
Complexity of Decision Trees for Boolean Operators

May 18, Afternoon: 13:30~14:45 & 15:00~16:15
7a: Nano Technology. Chair M. Kameyama
Hiroshi Inokawa and Yasuo Takahashi
Experimental and Simulation Studies of Single-Electron-Transistor-Based Multiple-Valued Logic
Ki-W. Song, S. H. Lee, D. H. Kim, K. R. Kim, J. Kyung, G. Baek, C.-A. Lee, J. D. Lee, .B.-G. Park
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic
Tetsuya Uemura and Masafumi Yamamoto
Proposal of Four-Valued MRAM based on MTJ/RTD Structure

7b: Modeling and Simulation. Chair B.J. Falkowski
Grosse, D., Fey, G., Drechsler, R.
Modeling Multi-Valued Circuits in System C
Elena N. Zaitseva
Dynamic Reliability Indices for Multi-State System
Marsha Chechik and Wendy MacCaull
CTH Model Checking over Logics with Non-Classical Negation

8a: Clone Theory. Chair M. Miyakawa
Machida, H., Rosenberg, I.G.
On the Centralizers of Monoids in Clone Theory
Pogosyan, G., Rosenberg, I.
Generation of the Post Lattice by Irreducible Clones
L. Haddad and G. E. Simons
Partial Clones Containing all Monotonic Idempotent Boolean Partial Functions

8b: Spectral Techniques. Chair D. M. Miller
Falkowski, B.J., Fu, Cheng
Family of Fast Transforms over GF(3) Logic
Mitchell A. Thornton
Spectral Transforms of Mixed-radix MVL Functions
René Krenz, Elena Dubrova and Andreas Kuehlmann
Fast Algorithm for Computing Spectral Transforms of Boolean and Multiple-Valued Functions on Circuit Representation

May 19, Morning: 9:10~10:10 & 10:30~11:45
9: Invited Talk. Chair H. Machida
Andrei Krokhin, Andrei Bulatov, and Peter Jeavons
Functions of multiple-valued logic and the complexity of constraint satisfaction: A short survey

10a: Applications. Chair Y. Hata
Claudio Moraga and Chongfu Huang
Learning subjective probabilities from a small data set
Fey, G., Kinder, S., Drechsler, R.
Using Games for Benchmarking and Representing the Complete Solution Space Using Symbolic Techniques
Popel, D.V.
From Continuous to Multiple-valued Data

10b: Decision Diagrams II. Chair G. Dueck
Miller, D.M., Drechsler, R.
Augmented Sifting of Multiple-Valued Decision Diagrams
J. T. Butler and T. Sasao
On the Average Path Length in Decision Diagrams of Multiple-Valued Functions
Rahardja, S., Xie, S.
Generalized Complex Spectral Decision Diagrams Using Unified Complex Hadamard Transform

Closing

*Day*	*Morning*		*Afternoon*
*May 16*	On-site Registration ULSI Workshop (10:00 ~ 17:10) program *Reception* (17:10 ~ 20:00)
*May 17*	Opening address 1. Invited Talk (Zadeh)	2a. Logic Design I 2b. Functional Expressions	3a. Fuzzy Logic 3b. LSI Design	4a. Logic Design II 4b. Logics and Algebras
*May 18*	5. Invited Talk (Asai)	6a. LSI Circuits 6b. Decision Diagrams I	7a. Nano Technology 7b. Modeling & Simulation	8a. Clone Theory 9b. Spectral Techniques *Plenary Meeting* *Banquet* (18:00 ~ 21:00)
*May 19*	9. Invited Talk (Krokhin)	10a. Applications 10b. Decision Diagrams II Closing	.