Last Update: April 1, 2004

	Thursday, May 20, 2004		Friday, May 21, 2004		Saturday, May 22, 2004
8:30	Coffee		Coffee		Coffee
8:45	(8:45) Opening Remarks (9:00) Session 1: Keynote Address		Session 5A: Circuits I	Session 5B: Fuzzy Logic and Learning	Session 9A: Single Electron Logic	Session 9B: Probability and Uncertainty
10:00	Break		Break		Break
10:20	Session 2A: Emerging Technologies	Session 2B: Logic	Session 6A: Reed Muller Expansions	Session 6B: Circuits II	Session 10A: Digital Design	Session 10B: Circuits III
12:00	Lunch		Lunch (visit Altera 12:30 - 13:20)		Closing Remarks
14:00	Session 3: Invited Address		Session 7: Round Table Discussion
15:00	Break		Break
15:20	Session 4A: Reversible Logic	Session 4B: Clones	Session 8A: MDDs	Session 8B: Mathematical Aspects
17:00			Break
17:15			Plenary Session
19:00			Banquet and Awards

Thursday, May 20, 2004

Session 1: Keynote Address	9:00 - 10:00
Jonathan Rose Hard vs. Soft: The Central Question of Pre-Fabricated Silicon

Break (10:00 - 10:20)

Session 2A: Emerging Technologies	10:20 - 12:00
Tsuji, Waho Multiple-Input Resonant-Tunneling Logic Gates for Flash A/D Converter Applications Raychowdhury, Roy A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs Takahashi, Hanyu Multiple-Valued Multiple-Rail Encoding Scheme for Low-Power Asynchronous Communication Munirul, Kameyama Ultra-Fine-Grain Field-Programmable VLSI Using Multiple-Valued Source-Coupled Logic

Session 2B: Logic	10:20 - 12:00
Sofronie-Stokkermans Resolution-Based Decision Procedures for the Positive Theory of Some Finitely Generated Varieties of Algebras Aguzzoli Uniform Description of Calculi for All t-Norm Logics Kawaguchi, Miyakoshi Weakly Associative Functions on [0, 1] as Logical Connectives Gerla Automata over MV-Algebras

Lunch (12:00 - 14:00)

Session 3:Invited Address	14:00 - 15:00
Gilles Brassard Quantum Communication Complexity: A Survey

Break (15:00 - 15:20)

Session 4A:Reversible Logic

15:20 - 17:35

Khan, Perkowski, Khan Ternary Galois Field Expansions for Reversible Logic and Kronecker Decision Diagrams for Ternary GFSOP Minimization Kerntopf, Perkowski, Khan On Universality of General Reversible Multiple-Valued Logic Gates Miller, Dueck, Maslov A Synthesis Method for MVL Reversible Logic Al-Rabadi Reversible Fast Permutation Transforms for Quantum Circuit Synthesis Al-Rabadi Quantum Circuit Synthesis Using Classes of GF(3) Reversible Fast Spectral Transforms

Session 4B: Clones	15:20 - 17:35
Haddad, Lau On Partial Clones containing Maximal Clones Machida, Rosenberg Monoids Whose Centralizer is the Least Clone Pogosyan, Rosenberg Algebraic Properties of Totally Irreducible Elements of Clone Lattices Pantovic, Vojvodic Minimal Partial Hyperclones on a Two-Element Set Romov Some Properties of Local Partial Clones on an Infinite Set

Friday, May 21, 2004

Session 5A: Circuits I	8:45 - 10:00
Fukuda Signed Digit CMOS (SD-CMOS) Logic Circuits with Static Operation Yoon, Han, Choi, Hwang A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC

Session 5B: Fuzzy Logic and Learning	8:45 - 10:00
Mihai Optimizing the Defuzzifier Timing for the Fuzzy Control of a Servodrive Moraga A Metasemantics to Refine Fuzzy If-Then Rules Ngom, Simovici, Stojmenovic Evolution Strategy for Learning Multiple-Valued Logic Functions

Break (10:00 - 10:20)

Session 6A: Reed Muller Expansions	10:20 - 12:00
Falkowski, Lozano, Rahardja Fast Optimization of Fixed-Polarity Reed-Muller Expansions over GF(5) Adams, McGregor On the Optimisation of Reed-Muller Expressions Falkowski, Lozano, Rahardja Spectra Generation for Fixed-Polarity Reed-Muller Transform over GF(5) Stankovic, Moraga, Astola Derivatives for Multiple-Valued Functions Induced by Galois Field and Reed-Muller-Fourier Expressions

Session 6B: Circuits II

10:20 - 12:00

Mochizuki, Takeuchi, Hanyu Intra-Chip Address-Presetting Data-Transfer Scheme Using Four-Valued Encoding Park, Yoon, Yoon, Kim Design of Quaternary Logic Gate Using Double Pass-Transistor Logic with Neuron MOS Down Literal Circuit Teng, Bolton A Self-Restored Current-Mode CMOS Multiple-Valued Logic Design Technique and its Applications Mirmotahari, Berg A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic

Lunch (12:00 -14:00)

Session 7: Round Table Discussion	14:00 - 15:00
Multiple-Valued Logic: Challenges and Opportunities Moderator: D. Michael Miller, University of Victoria Panelists: Marek Perkowski, Portland State University Grant Pogosyan, International Christian University Tsutomu Sasao, Kyushu Institute of Technology Dan Simovici, University of Massachusetts Boston Zvonko Vranesic, University of Toronto Takao Waho, Sophia University

Break (15:00 - 15:20)

Session 8A: MDDs	15:20 - 17:00
Nagayama, Sasao On the Minimization of Average Path Lengths for Heterogeneous MDDs Jankovic, Stankovic, Drechsler Reduction of Sizes of Multi-Valued Decision Diagrams by Copy Properties Stankovic, Astola Edge-Valued Decision Diagrams for Multiple-Valued Functions Fey, Drechsler, Ciesielski Algorithms for Taylor Expansion Diagrams

Session 8B: Mathematical Aspects	15:20 - 17:00
Schweigert Polynomial Functions on a Central Relation Rudeanu, Simovici A Graph-Theoretical Approach to Boolean Interpolation of Non-Boolean Functions Ansotegui, Bejar, Cabiscol, Manya The Interface between P and NP in Signed CNF Formulas Kondo Characterization Theorem of Lattice Implication Algebras

Saturday, May 21, 2004

Session 9A: Single Electron Logic

8:45 - 10:00

Degawa, Aoki, Higuchi, Inokawa, Takahashi A Single-Electron-Transistor Logic Gate Family and its Application --- Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic Inokawa, Takahashi, Degawa, Aoki, Higuchi A Single-Electron-Transistor Logic Gate Family and its Application --- Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions Yanushkevich, Shmerko, Guy, Lu Three Dimensional Multiple Valued Circuits Design Based on Single-Electron Logic

Session 9B: Probability Uncertainty	8:45 - 10:00
Avron, Lev Non-deterministic Matrices Popel, Popel Controlling Uncertainty in Discretization of Continuous Data Morgan Many Valued Probability Theory

Break (10:00 - 10:20)

Session 10A: Digital Design

10:20 - 12:00

Iguchi, Sasao, Matsuura A Method to Evaluate Logic Functions in the Presence of Unknown Inputs Using LUT Cascades Dubrova A Polynomial Time Algorithm for Non-Disjoint Decomposition of Multiple-Valued Functions Abd-El-Barr, Al-Awami Iterative-Based Minimization of Unary 4-Value Functions for Current-Mode CMOS Realization Babu, Zaber, Islam, Rahman On the Minimization of Multiple-Valued Input Binary-Valued Output Functions

Session 10B: Circuits III

10:20 - 12:00

Munirul, Kameyama Multiple-Valued Source-Coupled Logic VLSI Based on Adaptive Threshold Control and its Applications Ishida, Homma, Aoki, Higuchi Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH Kimura, Pagiamtzis, Sheikholeslami, Hanyu A Study of Multiple-Valued Magnetoresistive RAM (MRAM) Using Binary MTJ Devices Berg, Aunet, Næss, Mirmotahari Basic Multiple-Valued Functions Using Recharge CMOS Logic

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