The 2nd International Workshop on Post-Binary ULSI Systems Date May 27 13:30-17:20, 1993 Place Hyatt Retgency Sacramento Chair Michitaka Kameyama(Tohoku University) Sponsorship Monbusho International Research Program (Joint Research) Toward next generation intelligent integrated systems, multiple-valued digital processing technology becomes more and more important from both theoreteical and practical points of views. Especially, the following subjects will be key targets in making pioneering research : (1) In deep submicron integrated circuits, revolutionary architecture is essential because of the heavy load of interconnections. (2) Large-scale design techniques will be essential because of the ultra- high-integration. (3) Fault tolerant design is essential because of many problems due to the ultra-high-integration. The goal of the Workshop is to discuss the above subjects, and we will get several new ideas and/or hints to continue exciting research works on post-binary ULSI systems. Program (tentative plan) Introduction: M.Kameyama (Tohoku University) 13:30-13:40 Part I System and Implementation 13:40-14:40 Prospects of nanoelectronic circuits in deep submicron age A. Taddiken (Texas Instruments Inc.) Prospects of future high-integration circuit technology D. Etiemble (University of Paris) Device-model-based post-binary electronics systems T. Hanyu (Tohoku University) Part II Large-scale design methodology for ULSI Systems 15:00-16:00 Recent development of logic design methodology T. Sasao (Kyusyu Institute of Technology) Next generation CAD tool for ULSI systems J. T. Butler (Naval Postgraduate School) Highly parallel logic design for ultra-high-speed ULSI processors M. Kameyama (Tohoku University) Part III Applications of ULSI Systems 16:20-17:20 Real-time applications in ULSI Systems K. C. Smith (University of Toronto) Neural and fuzzy network applications using multiple-valued logic O. Ishizuka (Miyazaki University) Artificial intelligence using multiple-valued logic M. Mukaidono (Meiji University)